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    • Advanced Interrupt Architecture
      • Contributors
      • Preface
      • Copyright
      • Introduction
      • Chapter 1. CSRs Added to Harts
      • Chapter 2. Incoming MSI Controller (IMSIC)
      • Chapter 3. Advanced PLIC (APLIC)
      • Chapter 4. Interrupts for Machine and Supervisor Levels
      • Chapter 5. Interrupts for Virtual Machines (VS Level)
      • Chapter 6. Interprocessor Interrupts (IPIs)
      • Chapter 7. IOMMU Support for MSIs to Virtual Machines
    • IOMMU
      • Copyright and License Information
      • Contributors
      • Preface
      • Introduction
      • Chapter 1. Data Structures
      • Chapter 2. In-memory Queue Interface
      • Chapter 3. Debug Support
      • Chapter 4. Memory-mapped Register Interface
      • Chapter 5. Software Guidelines
      • Chapter 6. Hardware Guidelines
      • Chapter 7. IOMMU Extensions
      • Chapter 8. Bibliography
    • Platform-Level Interrupt Controller
      • Changelog
      • Copyright and license
      • Contributors
      • Introduction
      • Chapter 1. RISC-V PLIC Operation Parameters
      • Chapter 2. Memory Map
      • Chapter 3. Interrupt Priorities
      • Chapter 4. Interrupt Pending Bits
      • Chapter 5. Interrupt Enables
      • Chapter 6. Priority Thresholds
      • Chapter 7. Interrupt Claim Process
      • Chapter 8. Interrupt Completion
    • Server SoC
      • Copyright and License
      • Contributors
      • Introduction
      • Chapter 1. Server SoC Requirements
      • Chapter 2. Bibliography
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RISC-V IOMMU Architecture Specification

RISCV

RISC-V IOMMU Architecture Specification

Version v1.0.1, Revised 2026-02-22

This document is in the Ratified state

No changes are allowed. Any desired or needed changes can be the subject of a follow-on new extension. Ratified extensions are never revised.
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